It is commonplace in the semiconductor art to desire to obtain various doped regions in a semiconductor substrate which have a predetermined size and location with respect to each other. In many situations doped regions of the same or opposite conductivity type must be spaced apart laterally by small but carefully controlled amounts. For example, buried collector regions and channel-stop regions in bipolar integrated circuits are generally desired to be located in close proximity but not touching. They must have precisely defined sizes. In such situations it is highly desirable to be able to locate the various doped regions in such a way that they self-align. This is generally accomplished by having the size and location of the various regions determined by a single master mask without need for intermediate precision alignment steps. If this can be achieved, smaller and more densely packed devices and integrated circuits can be fabricated. This is highly desirable.
A number of fabrication schemes for determining the size and location of critical device and circuit areas have been developed. A typical procedure is described in U.S. Pat. No. 4,199,380 to M. G. Farrell et al. However, the various prior art fabrication methods have a number of limitations. A particular weakness of prior art fabrication methods arises when it is necessary to provide buried doped regions within the device structure. Examples of such buried doped regions are buried collector regions and buried channel-stop regions in bipolar integrated circuits. Since the buried regions are generally covered by an opaque epitaxial layer, special provisions must be made for marking or delineating their location under the epitaxial layer in order that other device regions can be aligned therewith. The delineation methods currently in use are imprecise, subject to error, and a source of defects which adversely affect other device regions during device manufacture. Thus, there is a continuing need for improved means and methods for obtaining buried doped regions in semiconductor devices which avoid the problems associated with existing delineation schemes and which provide for self-alignment of multiple buried regions of the same or opposite doping.
Accordingly, it is an object of the present invention to provide an improved means and method for forming buried doped regions in semiconductor devices.
It is a further object of the present invention to provide an improved means and method for alignment of subsequent device regions to buried doped regions without need for delineation of the buried doped regions.
It is an additional object of the present invention to provide improved means and methods for avoiding the material defects introduced in epitaxial overlayers by prior art buried layer delineation means and methods.
It is a further object of the present invention to provide an improved means and method for obtaining more compact integrated circuit structures by eliminating the need for an alignment step in locating buried channel-stop regions with respect to buried collector regions.
It is an additional objective to achieve the above noted objectives simultaneously.
As used herein, the words "polycrystalline" or "poly" are intended to refer to all non-single crystal forms of solids. Further, as used herein, the words "dip etching" are intended to refer to all forms and means of blanket etching or blanket erosion, and are not intended to be limited merely to wet chemical etching techniques. As used herein the word "delineation" is intended to refer to topographical surface features which reveal the presence of a device region extending to or buried beneath the surface of a semiconductor substrate.